Dsp Trigger Serial Number

Contents • • • • • • • • • • • • Introduction A common question is whether C28x interrupts can be nested. This article explains how interrupt nesting can be achieved with simple changes to the interrupt service routine (ISR) code. This article assumes the reader is already familiar with the following: • C28x PIE module: control registers, vector table, PIE groups • C28x interrupt control registers: IER, IFR, INTM in particular. For more information on these topics please refer to the following: • Interrupts at the CPU level and how the CPU responds to an interrupt is documented in the • The contains information on C28x interrupts.

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• The peripheral interrupt expansion block (PIE) is described in the for a particular device family]] Interrupt Prioritization Hardware Prioritization Interrupts are automatically prioritized by the C28x hardware. Prioritization for all interrupts can be found in the System Control guide specific to the particular device family.

The following table shows the priority for multiplexed interrupts. Group 1, which corresponds to CPU INT1, has the highest priority. Within each group there are 8 interrupts with INTx.1 being the highest priority and INTx.8 having the lowest. Hardware Interrupt Priority Priority Group Interrupt Highest Group 1 INT1.1 Group 1 INT1.2. Group 1 INT1.8 Group 2 INT2.1 Group 2 INT2.2. Group 12 INT12.1 Group 12 INT12.2. Lowest Group 12 INT12.8 PIE Interrupt Organization The PIE block is organized such that the interrupts are in a logical order.

Interrupts that typically require higher priority, are organized higher up in the table and will thus be serviced with a higher priority by default. The interrupts in a 28x system can be categorized as follows (ordered highest to lowest priority): • Non-Periodic, Fast Response These are interrupts that can happen at any time and when they occur, they must be serviced as quickly as possible. Typically these interrupts monitor an external event. Such interrupts are allocated to the first few interrupts within PIE Group 1 and PIE Group 2.

This position gives them the highest priority within the PIE group. In addition, Group 1 is multiplexed into the CPU interrupt INT1. CPU INT1 has the highest hardware priority. PIE Group 2 is multiplexed into the CPU INT2 which is the 2nd highest hardware priority. • Periodic, Fast Response These interrupts occur at a known period, and when they do occur, they must be serviced as quickly as possible to minimize latency.

The A/D converter is one good example of this. The A/D sample must be processed with minimum latency. Such interrupts are allocated to the group 1 in the PIE table. Group 1 is multiplexed into the CPU INT1. CPU INT1 has the highest hardware priority. • Periodic These interrupts occur at a known period and must be serviced before the next interrupt. Some of the PWM interrupts are an example of this.